1. Field of the Invention
The disclosure relates to a composition for preventing from leaning a capacitor in a semiconductor device, and a method for manufacturing a capacitor using the same.
2. Description of the Related Art
As the demand for semiconductor devices increases, various techniques for manufacturing a capacitor with a high capacitance have been suggested.
In the capacitor, a dielectric film is interposed between a lower electrode as a storage node and an upper electrode as a plate node. The capacitance of the capacitor is proportional to the surface area of the electrode and the dielectric constant of the dielectric film, and it is inversely proportional to the gap between the electrodes (i.e., the thickness of the dielectric film). A method using a dielectric film with a large dielectric constant, a method for reducing the thickness of a dielectric film, a method for increasing the surface area of the lower electrode, and a method for reducing the gap between electrodes have been used to manufacture a capacitor with a high capacitance.
However, with an increasing degree of integration, the size of the semiconductor memory device has been gradually reduced. It is thus difficult to manufacture a capacitor with a sufficient capacitance. Accordingly, research has been steadily conducted to improve the structure of the storage node. Concave-type and cylinder-type capacitors with a three-dimensional structure have been developed as a solution. Recently, the cylinder-type capacitor using both the internal area and the external area as the node area has been more popularly used than the concave-type capacitor using only the internal area as the node area.
Hereinafter, a conventional method of manufacturing a capacitor for a semiconductor device will be explained with reference to the accompanying drawings. FIG. 1a and FIG. 1b briefly illustrate a manufacturing process for a three-dimensional cylinder-type capacitor according to a conventional method.
FIG. 1a shows that an interlayer insulating film 3 is formed over a semiconductor substrate 1 having a semiconductor circuit such as transistors (not shown) and bit lines (not shown), and the interlayer insulating film 3 is etched to form storage node contact holes (not shown) to expose part of the semiconductor substrate 1.
Then, the storage node contact holes are filled with storage node contact plugs 5. Moreover, a nitride film 7 used as an etching barrier film, and a capacitor oxide film 9 determining the height of a lower electrode are deposited sequentially on the top surface of the interlayer insulating film 3 containing the storage node contact plugs 5.
The capacitor oxide film 9 is dry etched to form a trench (not shown) used for a storage node, and then a lower electrode 11 used for a storage node is formed inside the trench.
FIG. 1b shows that the lower electrode 11 used for a storage node undergoes a chemical mechanical polishing process or an etch-back process until the capacitor oxide film 9 is exposed to isolate the remaining portions of the lower electrode 11.
FIG. 1c shows that the capacitor oxide film 9 is removed by a wet-dip out process, in which the resultant structure of FIG. 1b is immersed and wet etched at a room temperature of 23° C. for about 25 minutes. The wet etching solution is an HF/NH4F solution prepared by mixing deionized water and HF/NH4F (manufactured by Techno Semichem Co., Ltd, Product Name: LAL400) at a volume ratio of 20:1. The structure is then sufficiently washed with deionized water, and placed in a vapor of isopropyl alcohol to be dried.
However, a reduced or finer design rule has resulted in a decrease in floor space at the time of formation of the storage node of a cylinder-type capacitor. Therefore, in an attempt to secure the capacitance of the capacitor, the capacitor oxide film 9 is formed to greatly increase the surface area of the lower electrode 11. This causes an increase in the aspect ratio of the lower electrode 11.
Consequently, during the drying step for removing moisture infiltrated between the lower electrodes 11 during the wet-dip out process for removing the capacitor oxide film 9, surface tension occurring between adjacent lower electrodes 11 leads to the frequent occurrence of a leaning phenomenon 13 in which the lower electrodes come in contact with each other and are bridged, as illustrated in FIG. 2. Unfortunately, the leaning phenomenon worsens with a decrease in the distance (i.e., line width) between capacitors. A narrower line width floor for a capacitor or an increased capacitor height is a result of the size reduction of semiconductor devices. This problem results in serious failures during the manufacturing process, reducing final production yields of semiconductor memory devices.
So far, an aspect ratio of 11 is best for enabling the manufacturing of 60 nm devices. In order to satisfy that the capacitance required for the cell is larger than 25*10−15, particularly for the operation of a device having a line width of 50 nm or less, the aspect ratio is expected to be 20 or larger.